Low Power Analog Integrated Circuits Design for Implementation of Support Vector Machine Algorithm
Marios Gourdouparis
Abstract
This work presents an ultra low power, 0.6V power supply analog integrated circuit architecture for the implementation of a Support Vector Machine algorithm with on-chip learning capability. The system architecture and its basic building blocks are discussed, with novel circuit architectures being proposed for the implementation of multivariate Radial Basis Function Kernels. This is an ultra low power implementation, with all transistors operating in the subthreshold region. The proposed architecture performs both learning and classification in an exclusively analog and massively parallel way. The efficiency and accuracy of the system is validated through performing SVM learning and classification with a real dataset. The inputs of the system vectors of 13 dimensions in the form of analog voltages. The classification accuracy diverges from a classic software SVM implementation by only 1%. The presented architecture was realized in TSMC 90 nm CMOS process and simulated using the Cadence IC Suite.