Design and Implementation of an 1-bit DAC
Adam Raptakis
Abstract
This work presents the design and actual implementation of an oversampling 1-bit digital to analog converter (DAC). High speed of operation and low additive phase noise were the primary goals of the circuit’s design. The 1-bit DAC is part of a Σ-Δ modulation system which was developed on Xilinx’s KC705 Evaluation Board (Kintex-7 FPGA Family). The system is clocked using high quality clock signals generated by the 1-bit DAC circuit. An external reference high-performance oscillator is used for clock signal generation. The 1-bit DAC is sampling and reclocking the FPGA’s 1-bit output data signal with an ultra-low jitter clock signal. The goal is to significantly reduce the phase noise of the data signal. The frequency and phase of each clock signal can be configured via a microcontroller in order to achieve perfect timing in the sampling process. The FPGA - DAC system can operate with clock frequency up to 500 MHz. The necessary simulations for impedance matching were carried out in Advanced Design Systems. This manuscript consists of five chapters. The 1st chapter is a brief introduction to the analogto-digital and digital-to-analog conversion. The 2nd chapter is an analysis of the advantages and the basic concepts of oversampling converters, such as noise shaping and Σ-Δ modulation. In the 3rd chapter the phase noise in oscillators as well as the impact of jitter on data conversion systems are described. The 1-bit DAC circuit is presented in the 4th chapter along with information about the components used and the design of the transmission lines. Finally, the 5th chapter exhibits the measurement results concerning the performance of the implemented 1-bit DAC circuit.