Implementation Of A Fully-Digital Analog Video VHF Transmitter in FPGA
Konstantinos Vasileiou
Abstract
In the context of this work, an FPGA circuit was constructed, implementing an all-digital video television transmitter, encoding Phase Alternating Line analog protocol. The circuit description was made using Verilog hardware description language and a Xilinx entry level FPGA board was used. The technical features of the circuit include: Video capturing algorithms using a VGA 640x480 pixel, 30 fps camera, RAM based frame buffer, PAL encoding algorithms, amplitude modulation and multi to single-bit quantization using random number dithering techniques. During the design process, main concern, apart from the flawless design, was a design that used the minimum resources on the FPGA board and could easily transposed onto an ASIC circuit. The current work has been accepted and will be presented in the joint UFFC, EFTF and PFM ΗΔΔΔ Symposium which will be held in Prague on 21-25 of July 2013. A poster and a live demo will be presented, and a paper explaining this thesis work have been submitted.