Analysis and Design of a CMOS Chopper Multiplier
Dimitrios Baxevanakis
Abstract
This work presents the analysis and design of a CMOS Chopper Multiplier as an autonomous analog block for processing low-amplitude low-frequency signals, with particular emphasis on achieving low output noise. The multiplier’s operation is based on chopper stabilization and the MOS Translinear Principle, while its implementation will be experimentally examined at this stage by means of the Cadence Custom IC Design Tool in TSMC 0.18 µm process.