Implementation of Learning Vector Quantization Algorithm on Low Power Analog Integrated Circuits for Interdisciplinary Applications
Emmanouil Serlis
Abstract
The goal of this diploma thesis is the implementation of the machine learning algorithm Learning Vector Quantization on ultra low-power analog integrated circuits. The designed architecture of the circuit - based on the algorithm’s structure - is presented in detail below, along with an analysis of the individual circuit components that constitute the classification system. Specifically, the fundamental elements of the integrated classifier are the Bump circuit for robust multidimensional distance metric generation, as well as the Winner-Take-All circuit for the final classification decision. This architecture is contrasted with an alternative implementation of the algorithm which includes a Euclidean distance circuit, with the final decision being made by a Loser-Take-All circuit. Furthermore, in classification tasks where the inputs need to be digital, the analog classifier can be extended through the incorporation of low-power digital circuits such as Digital-to-Analog converters and decoders. The implementation and training of the model, with the aim of determining the parameters for circuit implementation, are carried out using the Python programming language and the scikit-learn library. The hardware classifier is validated using three datasets and the comparative results between hardware and software are presented. The implementation and simulation of the circuit were conducted using the Cadence IC Suite design software in TSMC 90 nm CMOS process technology.