Design of a Direct Conversion 2.7GHz Receiver for LTE/4G in TSMC 90nm
Filippos Gozadinos
Abstract
This thesis presents the design of a CMOS RF front-end receiver for operation in Long Term Evolution (LTE)/4G, making use of the Direct Conversion architecture. The operating frequency is 2.7GHz. The three main stages are being designed which are the low noise amplifier (LNA), the mixer, and a typical single-pole filter with a real Opamp. We make use of the professional Cadence Virtuoso platform in order to design and simulate the circuits in TSMC 90nm technology. The total LNA/Mixer gain is 45.6 dB, while a -22.58 dBm IIP3 is being achieved. The Noise Figure is 1.75 dB, while the 1-dB Compression Point is -34.5 dBm.