Analysis and FPGA Implementation of a Single-Bit Two-Step Look-Ahead ΔΣ Modulator
Athanasios Orfanos
Abstract
In this paper we study a single bit ΔΣ Digital to Digital Converter (DD).Its input is a digital signal, a sequence consisting of many bits while in itsoutput this signal is depicted from a sequence of one just bit, {+1, −1}.The gain from this signal modulation is the given linearity from the output{+1, −1}, allowing us to forget the multi-bit Digital to Analog Converter(DAC). Recovery of the original signal can be done with just a lowpass filter.As multi-bit DAC by definition consists of many quantization levels, anyimperfections in the analog part (capacitors, resistors) will affect the valueof the levels entering nonlinear phenomena and attributing in this way themodulator. However with just two quantization levels, the error in the signalrepresentation will be very large. To offset the high error is required veryhigh sampling rate.For the implementation of the ΔΣ modulator is not used any widespreadtopology but the Multi-Step Look-Ahead (MSLA) ΔΣ modulator, a new proposal by the PhD student Charis Basetas and the assistant prof. Paul-PeterSotiriadi. The difference to conventional ΔΣ is that the calculation of output {+1, −1} results from the minimization of a cost function looking stepsahead. This paper examines the MSLA for two steps ahead. Also showsthe optimal architecture for the implementation of this modulator and also acomprehensive analysis is made for the calculation of the number of bits foreach signal in order to its application in real circuit to be efficient. Finally weimplemented the specific ΔΣ modulator on fpga and we observed the resultsin the spectrum analyzer.